Services

Focused help where products stall.

Engineering help for the points where medical devices get stuck. If your problem doesn't fit neatly into one of these, talk to us anyway.

Medical Device Reliability & Risk Assessment

  • Design for reliability
  • FMECA
  • Weibull life-data analysis
  • HALT and quantitative ALT
  • reliability demonstration

The challenge

There's no defensible number for how long the device will last in the field, and returns show failures the design files don't explain. Late failure modes end up as complaints, CAPAs and new hazards in the risk file.

How we solve it
  1. Translate the use profile, duty cycle and environment into quantitative reliability requirements, such as B10 life or reliability at a stated confidence over the service life, and allocate them to subsystems.
  2. Build a reliability block diagram and component-level FMECA to locate single points of failure and critical-to-reliability parts.
  3. Analyze field, complaint and test data with Weibull life-data methods to separate early-life, random and wear-out failure modes (shape parameter β < 1, ≈ 1 and > 1).
  4. Plan HALT to find operating and destruct margins, and quantitative accelerated life tests built on physics-of-failure models: Arrhenius for temperature, Coffin-Manson for thermal cycling, Peck for temperature and humidity.
  5. Size reliability demonstration tests statistically. For example, a zero-failure success-run plan needs 59 units to show 95% reliability at 95% confidence.

Standards we work toISO 14971:2019 · IEC 60812 (FMEA/FMECA) · IEC 61078 (reliability block diagrams) · IEC 61649 (Weibull analysis) · IEC 62506 (accelerated testing)

What you receive
  • Quantified reliability requirements and allocation
  • FMECA ranked by severity and occurrence, with critical-to-reliability items
  • Life-data analysis report with failure-mode classification
  • HALT, ALT and demonstration test plans with sample sizes and acceleration models
  • A prioritized list of design actions

Manufacturing Test Strategy & Architecture

  • DFT review
  • ICT
  • flying probe
  • IEEE 1149.1 boundary scan
  • SPI/AOI/AXI
  • functional test
  • yield analysis

The challenge

Yield is slipping, defects surface at system test or in the field, and nobody can say what each test stage actually catches. The further a defect travels, the more it costs to find.

How we solve it
  1. Build the defect universe for each assembly from the BOM, netlist and process: shorts, opens, missing, wrong or misoriented parts, solder-joint quality and functional faults.
  2. Score coverage stage by stage with a structured model (PCOLA/SOQ/FAM) across SPI, AOI, AXI, ICT or flying probe, boundary scan and functional test, and expose gaps and overlaps.
  3. Review design for testability: test-point access and probe pitch, JTAG chain integrity (IEEE 1149.1/1149.6), power sequencing and built-in self-test hooks.
  4. Analyze yield and failure Paretos (first-pass yield, rolled throughput yield, DPMO) to separate process defects from design-margin failures.
  5. Define the test architecture for the volume and change rate: flying probe for low volume and frequent ECOs, ICT for stable high volume, functional test as the release gate.
  6. Specify test method validation: gauge R&R for parametric limits, and seeded-defect or known-bad-board checks to confirm detection.

Standards we work toIEEE 1149.1 · IEEE 1149.6 · IPC-A-610 · IPC J-STD-001 · ISO 13485:2016 §7.5.6 (process validation)

What you receive
  • Coverage matrix by defect class and test stage, with gaps and overlaps
  • DFT findings with specific schematic and layout changes
  • Recommended test architecture, station and fixture concept
  • Test-limit rationale and test method validation plan
  • Yield actions ranked by expected impact

Quality & Risk Engineering

  • ISO 14971:2019
  • ISO/TR 24971
  • PHA
  • DFMEA, PFMEA and use-related analysis
  • fault tree analysis
  • verification planning

The challenge

The risk file was built late, FMEAs stand in for hazard analysis, and risk controls aren't traced to verification. Auditors find it, and every design change becomes harder to assess.

How we solve it
  1. Establish or audit the risk management plan, including risk acceptability criteria and the method for evaluating overall residual risk.
  2. Build the hazard analysis top-down (hazards, sequences of events, hazardous situations, harms) and complement it bottom-up with DFMEA, PFMEA and use-related analysis aligned with IEC 62366-1.
  3. Apply fault tree analysis to critical top events, including combinations of failures that a single-fault FMEA does not capture.
  4. Trace every risk control to a requirement, a design output and a verification activity, with defined acceptance criteria and statistically justified sample sizes.
  5. Plan verification of risk-control effectiveness, and connect production and post-production information (complaints, NCRs, field data) back to the risk file.

Standards we work toISO 14971:2019 · ISO/TR 24971:2020 · IEC 62366-1 · IEC 61025 (fault tree analysis) · IEC 60601-1 (essential performance)

What you receive
  • Updated risk management plan and hazard analysis
  • DFMEA and PFMEA aligned to the current design revision
  • Fault trees for critical hazards
  • Requirement-to-risk-to-verification traceability matrix
  • Verification plan with acceptance criteria and sample-size rationale
  • Gap report against ISO 14971:2019

Product Readiness & Prototype-to-Production Scale-Up

  • Design transfer (ISO 13485 §7.3.8)
  • DFM/DFA
  • tolerance analysis
  • process validation (IQ/OQ/PQ)
  • test method validation
  • supplier readiness

The challenge

The prototype works on the bench, but specifications, tolerances, test methods and suppliers aren't ready for repeatable production. Under ISO 13485 and the FDA QMSR, design outputs must be proven manufacturable before transfer.

How we solve it
  1. Run a structured readiness review across design, documentation, manufacturing process, test, supply chain and quality system, scoring each area against objective evidence.
  2. Review DFM/DFA and tolerance stack-ups against actual process capability, and identify critical-to-quality characteristics.
  3. Determine which processes need validation because their output can't be fully verified by later inspection, and plan IQ/OQ/PQ in line with GHTF SG3/N99-10.
  4. Confirm that test methods are validated (gauge R&R, attribute agreement analysis) and that risk controls from the risk file appear in the production specifications.
  5. Assess supply-chain risk: single-source and long-lead parts, obsolescence and incoming inspection.
  6. Define pilot-build entry and exit criteria with capability targets, such as Cpk ≥ 1.33 on critical characteristics.

Standards we work toISO 13485:2016 §7.3.8 · 21 CFR 820 (QMSR) · GHTF SG3/N99-10 (process validation) · ISO 14971:2019

What you receive
  • Readiness scorecard by area, with supporting evidence
  • Prioritized gap list with owners and closure criteria
  • Process validation master plan and test method validation list
  • Critical-to-quality characteristics with capability targets
  • Pilot-build plan and design transfer checklist

AI-Assisted Engineering Intelligence

  • Evidence consolidation
  • failure and complaint analytics
  • traceability gap detection
  • engineer-reviewed decision support

The challenge

Test reports, logs, NCRs, CAPAs and complaints live in different systems, so recurring failure patterns stay hidden. Reading across thousands of records by hand is slow, and unchecked AI output isn't evidence.

How we solve it
  1. Inventory the evidence sources and agree which records are in scope, under NDA and within your data-handling requirements.
  2. Use AI tools to extract, normalize and cluster records: failure descriptions, test results, log signatures and complaint narratives.
  3. Detect patterns such as recurring failure modes by lot, supplier, firmware version or test station, and gaps between requirements, risk controls and verification evidence.
  4. An engineer checks every finding against the source record before it is reported. Each conclusion cites the documents it rests on.
  5. Where tools are used inside your quality system, apply risk-based assurance consistent with the FDA's guidance on production and quality management system software.

Standards we work toISO 13485:2016 §4.1.6 (QMS software validation) · FDA guidance on production and quality management system software · ISO 14971:2019 (production and post-production information)

What you receive
  • A consolidated evidence summary with source references
  • Failure-signature and trend analysis
  • A list of traceability gaps
  • An engineer-reviewed findings memo with recommended actions

Systems Integration & Test Automation

  • Integration planning
  • interface control
  • verification test systems
  • hardware-in-the-loop
  • test automation
  • test-system qualification

The challenge

Subsystems pass on their own and fail together, and verification still depends on slow, manual procedures. Late integration issues push the schedule, and unqualified test equipment weakens the evidence it produces.

How we solve it
  1. Define the integration sequence, interface control documents and integration test points, from subsystem to system level.
  2. Design verification test systems: instrumentation, fixtures, data acquisition, and hardware-in-the-loop simulation for conditions that are unsafe or impractical to create on the bench.
  3. Automate repeatable verification and regression tests, with results traced to requirement IDs.
  4. Qualify the test system: measurement uncertainty, gauge R&R, and software validation proportional to risk.
  5. Plan for test-station reuse across verification, production and service.

Standards we work toIEC 60601-1 · IEC 62304 · ISO 13485:2016 §7.6 (monitoring and measuring equipment) · FDA guidance on production and quality management system software

What you receive
  • Integration plan and interface test matrix
  • Test system architecture and fixture specifications
  • Automated test framework with requirement-traced reports
  • Test system qualification and validation protocols

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